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Instruction set architectures
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#	Item
501	Microsoft PowerPoint - hotchips5 [Read-Only] Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:49:15 Tensilica Instruction set architectures Acorn Computers ARM architecture GNU Compiler Collection EnSilica Compiler Software Computing Programming language implementation
502	DL205 User Manual Volume 2 of 2 D2–USER–M 1 Vol 2: Table of Contents Add to Reading List Source URL: users.obs.carnegiescience.edu Language: English - Date: 2009-09-25 15:59:26 Microcontrollers Computing Electronics Instruction set architectures Central processing unit ARM architecture
503	:tf/b The CLIPPER® C4 Chipset A Superpipelined, Superscalar Processor Howard Sachs Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:12 Parallel computing Superscalar Central processing unit Scalar processor Instruction set architectures R10000 Alpha 21264 Computer architecture Computer hardware Computing
504	A Parallelizing Compiler for UltraSPARC Chris Aoki Peter Damron Kurt Goebel Vinod Grover Xiangyun Kong Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:47:36 Instruction set architectures Microprocessors CPU cache Cache Computer memory UltraSPARC SPARC Processor register Computer hardware Computer architecture Central processing unit
505	5.5 GFLOPS Vector Units for “Emotion Synthesis” System ULSI Engineering Laboratory, TOSHIBA Corp. A.Kunimatsu, N.Ide, T.Sato, Y.Endo, H.Murakami, T.Kamei, M.Hirano Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:49:08 Parallel computing Very long instruction word Emotion Engine 64-bit Instruction set 128-bit Computer architecture Instruction set architectures Central processing unit
506	__ ___________________________VME – QuicKit Telephony_ The modular design of our QuicKit product line makes it possible to prototype high-performance, Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 2002-06-04 16:04:39 IEEE standards Instruction set architectures MIPS architecture VMEbus Computing Backplane GreenSpring Computers MIPS Magnum Computer buses Computer architecture MIPS Technologies
507	A History of Modern 64-bit Computing Matthew Kerner [removed] Neil Padgett [removed] Add to Reading List Source URL: courses.cs.washington.edu Language: English - Date: 2007-03-05 13:51:30 Fabless semiconductor companies Instruction set architectures Classes of computers Intel Corporation Parallel computing Advanced Micro Devices Itanium X86 Intel Computer architecture Computing Computer hardware
508	Microsoft Word - EMC data sheet proposal.doc Add to Reading List Source URL: www.nxp.com Language: English - Date: 2015-02-23 09:31:16 Electronic engineering Embedded systems Instruction set architectures Integrated circuits ARM architecture Mbed microcontroller General Purpose Input/Output Joint Test Action Group I²C Electronics Computer architecture Microcontrollers
509	LPC11E6x 32-bit ARM Cortex-M0+ microcontroller; up to 256 kB flash and 36 kB SRAM; 4 kB EEPROM; 12-bit ADC Rev. 1.2 — 21 May[removed]Product data sheet Add to Reading List Source URL: www.nxp.com Language: English - Date: 2014-05-21 13:02:20 Microcontrollers Embedded systems Instruction set architectures ARM architecture Integrated circuits I²C Joint Test Action Group General Purpose Input/Output ARM Cortex-M Computer architecture Electronics Electronic engineering
510	Microsoft Word - 19-Final-Code-Generation.doc Add to Reading List Source URL: dragonbook.stanford.edu Language: English - Date: 2008-09-08 17:20:29 Subroutines Instruction set architectures Central processing unit MIPS architecture Assembly languages Calling convention Call stack Processor register Stack Computing Computer architecture Software engineering

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